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RM0008
Serial peripheral interface (SPI)
MSB justified standard
For this standard, the WS signal is generated at the same time as the first data bit, which is
the MSBit.
Figure 218. MSB Justified 16-bit or 32-bit full-accuracy length with CPOL = 0
CK
WS
Transmission
Reception
SD
MSB
May be 16-bit, 32-bit
LSB MSB
Channel left
Channel right
Data are latched on the falling edge of CK (for transmitter) and are read on the rising edge
(for the receiver).
Figure 219. MSB Justified 24-bit frame length with CPOL = 0
CK
WS
Transmission
Reception
SD
MSB
24-bit data
LSB
8-bit remaining
0 forced
Channel left 32-bit
Channel right
Figure 220. MSB Justified 16-bit extended to 32-bit packet frame with CPOL = 0
CK
WS
Transmission
Reception
SD
MSB
16-bit data
LSB
16-bit remaining
0 forced
Channel left 32-bit
Channel right
Doc ID 13902 Rev 9
603/995
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